4-1 tm an9824 RSLIC18 is a trademark of intersil corporation. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 spice model tutorial of the RSLIC18 ac loop the ac loop of the RSLIC18 refers to the voice band path which provides full duplex signal communication and impedance synthesis. the circuit operation is described here in as well as the macromodel used to simulate the ac performance of the device. the architecture is the same for all part numbers available in the RSLIC18 family of ringing subscriber line interface circuits. the information in this document applies to all part numbers of the RSLIC18 family: hc55180, hc55181, hc55182, hc55183 and hc55184. architectural description the complete ac response of the device is determined by a the dominant ac loop and a low frequency dc loop. the dc loop provides the loop current limit function and contributes to the ac characteristics below 400hz. the operation of the dc loop will not be discussed in detail, however the effects of this loop are included in the macromodel. voltage feed current sense the ac loop is designed around a voltage feed current sense architecture. the ac loop current is sensed across a pair of low value resistors which are in series with the tip and ring ampli?r outputs. these sense resistors are placed within the feedback loop of each ampli?r, compensating for voltage loss. all internal resistors use ratio relationships providing superb matching, temperature stability and gain accuracies. the voltage across each resistor is measured using a differential ampli?r, referred to as the sense ampli?r (sa). the sense ampli?r is con?ured as a dual differential ampli?r. the sense connections to the ampli?r are ipped?resulting in addition of metallic signals (ac voice and dc loop current) and cancellation of longitudinal currents. the output of the sense ampli?r drives an inverting ampli?r referred to as the transmit ampli?r (ta). the gain of the transmit ampli?r is set by the external component rs, which sets the synthesized impedance for the device. the output of the transmit ampli?r provides the 4-wire output of the device as well as the feedback required for impedance synthesis. the feedback signal for impedance matching is inverted with respect to the incoming voice signal at the receive input vrx. the receiver represents a unity gain current summing node. the voice signal at the vrx input and the feedback signal at the vtx output each drive internal resistors. the currents formed by the respective voltages and resistors are summed by a high impedance current summing junction. the sum of the currents are mirrored and drive the inverting terminal of the tip and ring ampli?rs. the mirrored output of the receiver sources tip current and sinks ring current, providing the differential 2-wire output for the device. figure 1. RSLIC18 ac signal transmission signal path tip ring + - -in vrx vtx r r + - + - + - 1:1 20 20 r 4r 4r 4r 4r r 8k r s c fb ta r vfb sa hc5518x r application note october 1998
4-2 functional description the functional blocks of the ac loop are the receiver, tip and ring ampli?rs, sense ampli?r and transmit ampli?r. receiver the receiver provides the current summing node for the voice signals from the codec (vrx) and the impedance matching feedback (vtx). the current generated by each voltage signal and internal 200k ? resistor is summed and mirrored to the tip and ring ampli?r inverting inputs. positive voltages at the receive input (vrx) will source current to the tip amp and sink current from the ring amp. tip and ring ampli?rs both ampli?rs are of voltage feedback design with a 200k ? feedback resistor. the voltage and current relationships of the receiver to tip and ring amplifier outputs is shown in figure 2. the 20 ? resistors are the sense resistors which provide the loop current information to the sense ampli?r. the sense resistor voltage drops are compensated by the feedback loop of each ampli?r. sense ampli?r the sense ampli?r is con?ured as a 4 input differential ampli?r with a voltage gain of 1/4. the differential input pairs are connected across the internal 20 ? sense resistors. current ?wing out of tip and into ring is the convention for positive loop current (i l ) ow. the sense connections across the sense resistors form an inverting relationship between the loop current ?w and the output voltage of the sense amp. figure 3 shows the sense ampli?r with connections to the sense resistors. the sense ampli?r output voltage as a function of the tip sense connections can be found by applying superposition to the circuit of figure 3. simplifying the terms in parenthesis leads to the tip sense differential relationship of equation 2. the voltage across the tip sense resistor is the loop current multiplied by the sense resistor as shown in equation 3. the voltage at the tip ampli?r output (v to ) is more positive than the tip sense connection voltage (v t ) as de?ed by the loop current ?w convention of figure 3. substituting the loop current term of equation 3 into the sense ampli?r output expression of equation 2 yields: applying the same superposition analysis to the ring sense connections results in the complete sense ampli?r output expression of equation 5. the final step in defining the sense amplifier functionality is to express the loop current in terms of the load impedance. since the loop from tip to ring represents a closed system the loop current out of tip equals the loop current into ring. therefore the voltage across any impedance in the loop will provide the loop current information. the loop impedance between tip and ring (v t and v r ) is the protection resistors (2r p ) and the load impedance (z l ). using this voltage and impedance relationship, the sense amplifier output voltage is rewritten as shown in equation 6. the last term of equation 6 represent the voltage gain relationship of the sense amp. transmit ampli?r the transmit ampli?r is a voltage feedback design with the noninverting terminal referenced to ground. it ampli?s the sense ampli?r output to achieve impedance synthesis. the output equation for the transmit ampli?r is provided below. the term rs is the external resistor used to program the synthesized impedance of the device. the value of rs is equal to 400 x z o . in addition to impedance matching, the transmit ampli?r drives the codec transmit interface. figure 2. receive interface tip ring vrx r r + - + - 1:1 20 20 r (+ ? v) (+ ? v) (- ? v) (+ ? i) (+ ? i) vb/2 figure 3. sense amplifier sensing connections tip ring + - + - + - 20 20 r 4r 4r 4r 4r r (+ ? i l ) (+ ? i l ) v sa v to v t v ro v r v sa t () v t r4r || 4r r 4r || + ------------------------------- - ?? ?? 1 r 4r ------- - + ?? ?? v to r 4r ------- - ?? ?? = (eq. 1) v sa t () 1 4 -- - v t v to () = (eq. 2) v to v t 20i l = (eq. 3) v sa t () 1 4 -- - v t v to () 1 4 -- - 20i l () 5 i l = = = (eq. 4) v sa v sa t () v sa r () 5 i l () 5 i l () 10i l = + = + = (eq. 5) i l v t v r z l 2r p + ------------------------ - = v sa v t v r () 10 z l 2r p + ------------------------ - = ? (eq. 6) v ta v sa r s 8000 ------------ - ?? ?? v sa 400z o 8000 --------------------- ?? ?? = = (eq. 7) application note 9824
4-3 spice macromodel analysis the spice macromodel represents entire the ac loop of the device. of the five functional blocks only the receiver is not modeled. the receiver does not contribute significantly to the device bandwidth and is modeled as an ideal current mirror. the four core amplifiers of the design are modeled by two or three pole circuits using voltage controlled voltage sources. low frequency effects of the loop current limit function are included in the model but will not be discussed in detail. the spice net list included at the end of the document should be compatible with any spice compatible simulation software. model diagram the macromodel diagram of figure 6 is very similar to the functional diagram of figure 1. the only differences are the addition of the dc loop current limit function and generic blocks representing the ampli?rs. the current mirror is modeled using a generic current controlled current source. amplifier models the primary ampli?r blocks of the architecture are the tip, ring, sense and transmit ampli?rs. each ampli?r will be discussed separately followed by simulation examples using the model. tip ampli?r the tip ampli?r is modeled with a three pole circuit. the open loop gain is 49740 or 94db and the open loop 3db bandwidth is 13hz. an internal compensation capacitor of 5.2pf in parallel with the feedback resistor of 200k ? forms a zero in the ampli?r response at 153khz. the model for the tip ampli?r is shown below. the non inverting input is indicated by (+), the inverting input by (-) and the output by (o). ring ampli?r the ring amplifier is modeled with a three pole circuit. the open loop gain is 59420 or 95db and the open loop 3db bandwidth is 12hz. an internal compensation capacitor of 8pf in parallel with the feedback resistor of 200k ? forms a zero in the amplifier response at 100khz. the model for the ring amplifier is shown below. the non inverting input is indicated by (+), the inverting input by (-) and the output by (o). figure 4. tip amplifier 3-pole model + - + - + - + - + - + - + - + - 11.9g 56k 55k 132k 1p 1p 1p g = 49740 5.2p g = 1 g = 1 g = 1 (o) ( - ) (+) + - + - + - + - + - + - + - + - 13.4g 65k 65k 155k 1p 1p 1p g = 59420 8p g = 1 g = 1 g = 1 (o) ( - ) (+) figure 5. ring amplifier 3-pole model tip (o) (+) ( - ) tip ring -in vrx vtx r r 1:1 20 20 r 4r 4r 4r 4r r 8k r s c fb r vfb r ring (o) ( - ) (+) sense (o) (+) ( - ) transmit (o) ( - ) (+) figure 6. ac loop macromodel diagram dc loop t_out t_sns ringrx tiprx application note 9824
4-4 s ense ampli?r the sense ampli?r is modeled with a two pole circuit. the open loop gain is 4716 or 73db and the open loop 3db bandwidth is 260hz. the model for the sense ampli?r is shown below. the non inverting input is indicated by (+), the inverting input by (-) and the output by (o). transmit ampli?r the transmit ampli?r is modeled with a two pole circuit. the open loop gain is 4151 or 72db and the open loop 3db bandwidth is 127hz. the model for the transmit ampli?r is shown below. the non inverting input is indicated by (+), the inverting input by (-) and the output by (o). the gains and component values used in the models were matched to the actual device level simulations of each ampli?r. lab measurements may vary due to component tolerances and process variations. simulation example - resistive load resistive matching is a misnomer, since the impedance being matched is in the voice band. however, resistive matching is the case when the device synthesizes an impedance to match a purely resistive load. this example will match the device to a 600 ? load impedance, which is the reference impedance for most north american telephony ac transmission speci?ations. device impedance synthesis the device synthesized impedance (z o ) is de?ed as the difference between the load impedance (z l ) and the sum of the protection resistance (r p ). typically the load impedance represents a combination of loop length and phone impedance, therefore a separate term for the loop length (ohms/foot) is not required. the external resistor, r s , which programs the synthesized impedance is calculated from the equation shown below. the resistor value used in the application circuit will be the standard component value nearest to the calculated value. g 42 simulation the g 42 frequency response of the device is simulated using the circuit of figure 9. the vrx input of the model is driven by an ac voltage source. the differential voltage across the 600 ? load is converted to single ended by the voltage controlled voltage source with a gain of 1. a db voltage probe was used to measure the magnitude and a phase voltage probe was used to measure the phase of the frequency response. expected results the g 42 results are predicted using the voltage divider relationship shown below. the magnitude of the frequency response in the voice band, 300hz to 3400hz, should be approximately 0db and the phase should be nearly 180 degrees. g 24 simulation the g 24 frequency response of the device is simulated using the circuit of figure 10. figure 7. sense amplifier 2-pole model + - + - + - + - + - + - 611m 92k 1p 1p g = 4716 g = 1 g = 1 (o) (-) (+) figure 8. transmit amplifier 2-pole model + - + - + - + - + - + - 1.25g 100k 1p 1p g = 4151 g = 1 g = 1 (o) ( - ) (+) z o z l 2r p 600 ? 235 ? () 530 ? = == (eq. 8) r s 400 z o 400 530 ? 212k ? = = = (eq. 9) figure 9. g 42 resistive load simulation circuit + - + - 600 ? 470nf g = 1 tip ring vrx vtx -in vfb RSLIC18 model 35 ? 35 ? 212k ? 470nf 10m ? g 42 2 z l z l 2r p z o ++ -------------------------------------- - 2 600 () 600 2 35 () 530 ++ ----------------------------------------------- - 1 == = (eq. 10) figure 10. g 24 resistive load simulation circuit + - + - 600 ? 470nf g = 2 tip ring vrx vtx -in vfb RSLIC18 model 35 ? 35 ? 212k ? 470nf application note 9824
4-5 the voltage controlled voltage source converts the single ended ac voltage source to a differential driver for the 2-wire interface. the 4-wire output voltage is measured at the transmit output, vtx, of the device. a db voltage probe was used to measure the magnitude and a phase voltage probe was used to measure the phase of the frequency response. expected results the g 24 results are predicted using the voltage divider relationship shown below. the magnitude of the frequency response in the voice band, 300hz to 3400hz, should be approximately -7.1db and the phase should be nearly 180 degrees. g 44 simulation the g 44 frequency response of the device is simulated using the circuit of figure 11. the vrx input of the mode is driven by an ac voltage source. the 4-wire output voltage is measured at the transmit output, vtx, of the device. a db voltage probe was used to measure the magnitude and a phase voltage probe was used to measure the phase of the frequency response. expected results the g 44 results are predicted using the voltage divider relationship shown below. the magnitude of the frequency response in the voice band, 300hz to 3400hz, should be approximately -7.1db and the phase should be nearly 180 degrees. simulation example - complex load most international telephony transmission requirements are de?ed around a complex 2-wire impedance. the most widely recognized form of the complex network is shown below as well as the device synthesis network to match the impedance. this simulation example will use the 2-wire complex network for china which is de?ed as r 1 = 200 ? , r 2 = 680 ? and c 2 = 100nf. device impedance synthesis when matching the device to a complex load the sum of the protection resistance is subtracted from the series resistor r 1 . the other components remain unchanged. the general form of the design equation is shown below. substituting actual component values results in the complex network to be synthesized by the device. typically the load impedance represents a combination of loop length and phone impedance, therefore a separate term for the loop length (ohms/foot) is not required. the external resistor, r s , which programs the synthesized impedance now takes the form of the complex network de?ed by r 1s , r 2s and c 2s . the resistor value used in the application circuit will be the standard component value nearest to the calculated value. g 42 simulation the g 42 frequency response of the device can be simulated using the circuit of figure 13. g 24 z o z l 2r p z o ++ -------------------------------------- - 530 600 2 35 () 530 ++ ----------------------------------------------- - 0.441 == = (eq. 11) figure 11. g 44 resistive load simulation circuit 600 ? 470nf tip ring vrx vtx -in vfb RSLIC18 model 35 ? 35 ? 212k ? 470nf g 44 z o z l 2r p z o ++ -------------------------------------- - 530 600 2 35 () 530 ++ ----------------------------------------------- - 0.441 == = (eq. 12) figure 12. typical complex impedance network 2-wire network r 1 r 2 c 2 synthesis network r 1s r 2s c 2s z o z l 2r p r 1 r 2 c 2 || + () 2r p () = = (eq. 13) z o 200 680 100n || + () 235 () 130 680 100n || + = = (eq. 14) r 1s 400 r 1 2r p () 400 130 () 52k ? = = = (eq. 15) r 2s 400 r 2 () 400 680 () 272k ? = = = (eq. 16) c 2s c 2 400 --------- - 100n 400 ------------- 250pf == = (eq. 17) figure 13. g 42 complex load simulation circuit + - + - 470nf g = 1 tip ring vrx vtx -in vfb RSLIC18 model 35 35 272k 470nf 10m 200 100n 680 250p 52k application note 9824
4-6 expected results though slightly cumbersome, the voltage divider relationship also applies to the complex matching gain. substituting the above terms into equation 19, the g 42 gain equation for complex matching is formed. cancelling the protection resistor terms in the denominator reduces the gain equation into the following simpli?d form. therefore for either resistive or complex matching the g 42 voltage gain will always be unity and the phase will be nearly 180 degrees. g 24 simulation the g 24 frequency response of the device can be simulated using the circuit of figure 14. expected results the g 24 results for complex matching are predicted using the voltage divider relationship shown below. substituting the above terms into equation 22, the g 24 gain equation for complex matching is formed. cancelling the protection resistor terms in the denominator and substituting terms reduces the gain equation to the frequency dependent form shown below. until now, all relationships have simpli?d to scalar terms and have not contained frequency dependent components. evaluating the gain at 1khz, results in a voltage gain of 0.459 and a phase of 178 degrees. simulation results will vary slightly due to device bandwidth. g 44 simulation the g 44 frequency response of the device can be simulated using the circuit of figure 15. expected results the g 44 results for complex matching are predicted using the voltage divider relationship shown below. since the g 44 gain has the same mathematical expression as the g 24 gain, the same frequency dependent gain equation applies to both. evaluating the gain at 1khz, results in a voltage gain of 0.459 and a phase of 178 degrees. simulation results will vary slightly due to device bandwidth. simulation results the following pages contain results for both simulation examples. the magnitude and phase response of each gain path is plotted from 10hz to 10khz. the model will accurately predict device frequency response up to 1mhz. in addition to the graphs, numerical data is also provided for reference. performing the above simulations is suggested when ?st using the model. the results obtained should agree with those provided herein. where: z l =r 1 + r 2 // c 2 r p =r p z o =(r 1 +r 2 // c 2 ) - (2r p ) where: z l =r 1 + r 2 // c 2 r p =r p z o =(r 1 +r 2 // c 2 ) - (2r p ) g 42 2 z l z l 2r p z o ++ -------------------------------------- - = (eq. 18) g 42 2 r 1 r 2 c 2 || + () r 1 r 2 c 2 || + () 2r p r 1 r 2 c 2 || + () 2r p () ++ ----------------------------------------------------------------------------------------------------------------------------- = (eq. 19) g 42 2 r 1 r 2 c 2 || + () r 1 r 2 c 2 || + () r 1 r 2 c 2 || + () + ------------------------------------------------------------------------------------ 1 == (eq. 20) figure 14. g 24 complex load simulation circuit 470nf tip ring vrx vtx -in vfb RSLIC18 model 35 35 272k 470nf 200 100n 680 250p 52k + - + - g = 2 g 24 z o z l 2r p z o ++ -------------------------------------- - = (eq. 21) g 24 r 1 r 2 c 2 || + () 2r p () () r 1 r 2 c 2 || + () 2r p r 1 r 2 c 2 || + () 2r p () ++ ----------------------------------------------------------------------------------------------------------------------------- = (eq. 22) where: z l =r 1 + r 2 // c 2 r p =r p z o =(r 1 +r 2 // c 2 ) - (2r p ) g 42 () r 1 2r p () r 2 1j c 2 r 2 + ------------------------------- + 2r 1 r 2 1j c 2 r 2 + ------------------------------- + ---------------------------------------------------------------------------- - = (eq. 23) figure 15. g 44 complex load simulation circuit 470nf tip ring vrx vtx -in vfb RSLIC18 model 35 35 272k 470nf 200 100n 680 250p 52k g 44 z o z l 2r p z o ++ -------------------------------------- - = (eq. 24) application note 9824
4-7 resistive matching simulation results figure 16. g 42 resistive matching magnitude response figure 17. g 42 resistive matching phase response figure 18. g 24 resistive matching magnitude response figure 19. g 24 resistive matching phase response figure 20. g 44 resistive matching magnitude response figure 21. g 44 resistive matching phase response table 1. resistive matching numerical results frequency g 42 g 24 g 44 magnitude (db) phase (deg) magnitude (db) phase (deg) magnitude (db) phase (deg) 10 4.46 179.9 -15.29 -113.0 -15.29 -113.0 30 2.64 166.8 -9.21 -141.9 -9.21 -141.9 100 0.48 171.5 -7.37 -166.9 -7.37 -166.9 300 0.06 177.1 -7.16 -175.9 -7.16 -175.9 1k 0.02 180.0 -7.14 -180.1 -7.14 -180.1 3k 0.08 182.5 -7.15 -183.8 -7.15 -183.8 10k 0.77 187.7 -7.34 -194.0 -7.34 -194.0 0 2 4 6 10 30 100 300 1k 3k 10k frequency (hz) mag (db) 10 30 100 300 1k 3k 10k frequency (hz) 160 170 180 190 phase (deg) 10 30 100 300 1k 3k 10k -4 -8 -12 -16 frequency (hz) mag (db) 10 30 100 300 1k 3k 10k -100 -150 -200 frequency (hz) phase (deg) 10 30 100 300 1k 3k 10k -4 -8 -12 -16 frequency (hz) mag (db) 10 30 100 300 1k 3k 10k -100 -150 -200 frequency (hz) phase (deg) application note 9824
4-8 complex matching simulation results figure 22. g 42 complex match magnitude response figure 23. g 42 complex match phase response figure 24. g 24 complex match magnitude response figure 25. g 24 complex match phase response figure 26. g 44 complex match magnitude response figure 27. g 44 complex match phase response 0 2 4 6 10 30 100 300 1k 3k 10k frequency (hz) mag (db) 10 30 100 300 1k 3k 10k frequency (hz) 170 175 180 185 phase (deg) 165 10 30 100 300 1k 3k 10k -5 -10 -15 frequency (hz) mag (db) 10 30 100 300 1k 3k 10k -100 -150 -200 freq (hz) phase (deg) 10 30 100 300 1k 3k 10k -5 -10 -15 frequency (hz) mag (db) 10 30 100 300 1k 3k 10k -100 -150 -200 frequency (hz) phase (deg) table 2. complex match numerical results frequency g 42 g 24 g 44 magnitude (db) phase (deg) magnitude (db) phase (deg) magnitude (db) phase (deg) 10 4.70 179.2 -14.7 -113.8 -14.7 -113.8 30 2.74 165.9 -8.76 -143.0 -8.76 -143.0 100 0.49 171.1 -7.02 -167.6 -7.02 -167.6 300 0.07 177.2 -6.84 -176.8 -6.84 -176.8 1k 0.12 180.4 -6.92 -182.1 -6.92 -182.1 3k 0.42 181.0 -7.34 -187.1 -7.34 -187.1 10k 0.69 178.5 -8.50 -194.0 -8.50 -194.0 application note 9824
4-9 spice net list the following is the complete net list for the macromodel. notations have been added to the listing to assist in decoding the net list. *spice net list* *components at amplifier block interconnect level* r_u1_r1 $n_0002 $n_0001 200k r_u1_r2 $n_0002 $n_0027 200k r_u1_r3 $n_0035 $n_0043 200k r_u1_r4 $n_0035 $n_0036 20 r_u1_r5 $n_0003 $n_0044 200k r_u1_r6 $n_0003 $n_0010 20 r_u1_r7 $n_0036 $n_0029 600k r_u1_r8 $n_0003 $n_0029 600k r_u1_r9 $n_0010 $n_0028 600k r_u1_r10 $n_0035 $n_0028 600k r_u1_r11 $n_0028 0 150k r_u1_r12 $n_0029 $n_0034 150k r_u1_r13 $n_0034 $n_0004 8k f_u1_f4 $n_0043 $n_0044 vf_u1_f4 -1 vf_u1_f4 $n_0002 $n_0005 0v r_u1_r23 0 $n_0005 1 v_u1_v1 $n_0014 0 -12v *ring ampli?r model components* e_u1_hs1_e8 $n_0006 0 $n_0014 $n_0044 59420 e_u1_hs1_e9 $n_0008 0 $n_0007 0 1 e_u1_hs1_e10 $n_0010 0 $n_0009 0 1 r_u1_hs1_r24 $n_0006 $n_0007 13.4g r_u1_hs1_r25 $n_0011 $n_0009 65k c_u1_hs1_c2 0 $n_0012 1p c_u1_hs1_c3 0 $n_0009 1p r_u1_hs1_r27 $n_0008 $n_0013 65k c_u1_hs1_c5 0 $n_0013 1p e_u1_hs1_e12 $n_0011 0 $n_0013 0 1 r_u1_hs1_r29 $n_0012 $n_0007 155k c_u1_hs1_c6 $n_0010 $n_0044 8p *tip ampli?r model components* e_u1_hs2_e8 $n_0015 0 $n_0014 $n_0043 49740 e_u1_hs2_e9 $n_0017 0 $n_0016 0 1 e_u1_hs2_e10 $n_0036 0 $n_0018 0 1 r_u1_hs2_r24 $n_0015 $n_0016 11.9g r_u1_hs2_r25 $n_0019 $n_0018 55k c_u1_hs2_c2 0 $n_0020 1p c_u1_hs2_c3 0 $n_0018 1p r_u1_hs2_r27 $n_0017 $n_0021 56k c_u1_hs2_c5 0 $n_0021 1p e_u1_hs2_e12 $n_0019 0 $n_0021 0 1 r_u1_hs2_r29 $n_0020 $n_0016 132k c_u1_hs2_c6 $n_0036 $n_0043 5.2p *transmit ampli?r model components* e_u1_hs3_e8 $n_0023 0 0 $n_0022 4151 e_u1_hs3_e9 $n_0025 0 $n_0024 0 1 e_u1_hs3_e10 $n_0027 0 $n_0026 0 1 r_u1_hs3_r24 $n_0023 $n_0024 1.25g r_u1_hs3_r25 $n_0025 $n_0026 100k c_u1_hs3_c2 0 $n_0024 1p c_u1_hs3_c3 0 $n_0026 1p *sense ampli?r model components* e_u1_hs4_e8 $n_0030 0 $n_0028 $n_0029 4716 e_u1_hs4_e9 $n_0032 0 $n_0031 0 1 e_u1_hs4_e10 $n_0034 0 $n_0033 0 1 r_u1_hs4_r24 $n_0030 $n_0031 611m r_u1_hs4_r25 $n_0032 $n_0033 92k c_u1_hs4_c2 0 $n_0031 1p c_u1_hs4_c3 0 $n_0033 1p *dc loop current model components* g_u1_u4_g1 $n_0037 0 $n_0035 $n_0036 69.4e-6 i_u1_u4_i1 $n_0038 0 dc 34.375e-6 r_u1_u4_r1 $n_0039 0 17k r_u1_u4_r2 $n_0041 $n_0040 100k c_u1_u4_c2 0 $n_0039 4.7u g_u1_u4_g2 $n_0042 0 $n_0036 $n_0035 69.4e-6 r_u1_u4_r6 0 $n_0042 10e6 r_u1_u4_r7 0 $n_0038 10e6 r_u1_u4_r8 0 $n_0037 10e6 d_u1_u4_d6 $n_0042 $n_0038 dbreak d_u1_u4_d8 $n_0037 $n_0038 dbreak g_u1_u4_g6 $n_0043 $n_0044 $n_0039 0 58.823e-6 g_u1_u4_g8 $n_0039 0 $n_0040 0 4e-3 d_u1_u4_d10 $n_0038 $n_0045 dbreak r_u1_u4_r33 0 $n_0045 50k e_u1_u4_e3 $n_0041 0 $n_0045 0 1 i_u1_u4_i17 $n_0039 0 dc 20u g_u1_u4_g10 $n_0039 0 $n_0046 0 2.5e-6 v_u1_u4_v16 $n_0046 0 -24 r_u1_u4_r40 0 $n_0040 100e15 v_u1_v1 $n_0014 0 -12v *end of subcircuit the ?es required to load the model in microsim pspice are located on our website at: www.intersil.com. application note 9824
4-10 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com application note 9824
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